This invention relates to a semiconductor device having a plurality of integrated circuit die in a stack and, in particular, to means for interconnecting the die in the stack.
The continued increase in the density of integrated circuits, i.e. the number of transistors per square centimeter of die area, whets rather than satisfies the appetite of industry for further increases. One solution to the problem is to stack several die one on another within a single package. (For the sake of description only, the stack is assumed vertical, with the die parallel to the upper and lower surfaces. Thus, the side of the stack contains the edges of the die. The die are assumed to be rectangular. "Die" are also referred to as "chips" in the industry.)
As recognized in the art, there are several difficulties with this approach. A first difficulty with stacked die is the limitation imposed by the heat generated by each die. When packaged singly and mounted on a printed circuit board, the heat generated by the die during operation is relatively easily dissipated because the die are spread out across the printed circuit board. When grouped together, particularly in a stack, power dissipation restricts the type of die that can be stacked to relatively low power integrated circuits.
It is generally assumed in the art that the primary cooling mechanism for the die is conductive cooling through the leads from the die, with some radiative cooling from the leads. Thus, organizing the die in a stack according to their power dissipation, e.g. putting the die generating the most heat on top of the stack, is not effective. Further, most applications use identical die in the stack, e.g. memory devices. One can obtain, for example, a four-fold increase in memory size on a given size printed circuit board by using stacked die.
One solution to the problem of heat dissipation is described in U.S. Pat. No. 5,051,865, in which one side of the stack is provided with electrical connections and the opposite side of the stack is provided with a heat sink to which the die are thermally, but not electrically, connected. A problem with this approach is that one side of the stack is devoid of electrical connections, which limits the number of leads that the die can have and, to some extent, limits the geometry of the die.
An ancillary problem to heat dissipation is stress in the die due to thermal cycling. Specifically, the temperature coefficient of expansion for the die should be matched by the package so that the die are not compressed or distorted due to temperature changes. In packages of the prior art, the die are mechanically and electrically connected to the sides, e.g. by soldering. If the sides, top, and bottom of the package do not have the same, or nearly the same, temperature coefficient of expansion as the die, then the die can become stressed as their temperature rises. This can lead to contact separation or fracture of the interconnect layers on the die.
A second difficulty with stacked die is the density of the die themselves. Power supply, ground, control signals, and input and output signals must all be supplied to all die in the stack. The number of leads depends on the particular die but can be as many as four hundred. Thus, the device used to interconnect the die must have at least this number of conductors. In theory, the conductors can be made arbitrarily thin. In practice, thin conductors limit the amount of current that can be carried by the conductors, limit the amount of cooling through the conductors, and make it difficult to align the leads on the die with the conductors which interconnect the die.
The device used to interconnect the die has taken several forms. In U.S. Pat. No. 5,006,925, chip carriers form the sides of the stack and are soldered together. There are holes in the chip carriers for ventilation. In U.S. Pat. No. 4,983,533, a plurality of die are glued together and electrically connected by solder bumps on a silicon substrate attached to the side of the stack.
U.S. Pat. No. 4,935,005 discloses depositing conductors on the sides of the already formed stack to contact the leads from the die. The die are attached to TAB (tape automatic bonding) leadframes, mounted on an insulating member having a recess for receiving the die. The tape is used to align the die while the die and insulating members are glued together. The portions of the tape extending beyond the insulating member are then removed and the conductors are deposited. A TAB leadframe is also disclosed for connecting the stack to a small circuit board which serves as the bottom of the package and which carries a plurality of conductive pins.
Each stage of an assembly process introduces defects which must be detected and corrected. Taking apart stack packages of the prior art is difficult or impossible to do non-destructively. Depending upon the number and type of die used, it is often less expensive to throw a defective stack away rather than to repair it.
In view of the foregoing, it is therefore an object of the invention to provide an improved package for stacked semiconductor die.
Another object of the invention is to provide a package for stacked semiconductor die which can be disassembled.
A further object of the invention is to provide a method for packaging stacked semiconductor die.
Another object of the invention is to provide a resilient connection between semiconductor die and the sides of a stack.
A further object of the invention is to provide a package for stacked semiconductor die in which the temperature coefficient of expansion of the package need not be matched to that of the die.
Another object of the invention is to provide a package for stacked semiconductor die which enables improved fluid flow around the die for cooling the die.